Studies of the execution behavior of high-level language programs have provided guidance in designing a new type of processor architecture：the reduced instruction set computer（RISC）．Assignment statements predominate，suggesting that the simple movement of data should be optimized．There are also many IF and LOOP instructions，which suggest that the underlying sequence control mechanism needs to be optimized to permit efficient pipelining．Studies of operand reference patterns suggest that it should be possible to enhance performance by keeping a moderate number of operands in registers．
These studies have motivated the key characteristics of RISC machines：（1）a limited instruction set with a fixed format．（2）a large number of registers or the use of a compiler that optimizes register usage，and（3）an emphasis on optimizing the instruction pipeline．
The simple instruction set of a RISC lends itself to efficient pipelining because there are fewer and more predictable operations performed per instruction．[1] A RISC instruction set architecture also lends itself to the delayed branch technique，in which branch instructions are rearranged with other instructions to improve pipeline efficiency．
Although RISC systems have been defined and designed in a variety of ways by different groups，the key elements shared by most designs are these：
．A large number of general-purpose registers，or the use of compiler technology to optimize register usage
．A limited and simple instruction set
．An emphasis on optimizing the instruction pipeline
Table 2-1 compares several RISC and non-RISC systems.
1．Instruction Execution Characteristics
To understand the line of reasoning of the RISC advocates，we begin with a brief review of instruction execution characteristics．The aspects of computation of interest are as follows：
• Operations performed：These determine the functions to be performed by the processor and its interaction with memory．
• Operands used：The types of operands and the frequency of their use determine the memory organization for storing them and the addressing modes for accessing them．
• Execution sequencing：This determines the control and pipeline organization．
2．The Use of A Large Register File [2]
The reason that register storage is indicated is that it is the fastest available storage device，faster than both main memory and cache．The register file is physically small，generally on the same chip as the ALU and control unit，and employs much shorter addresses than addresses for cache and memory．Thus，a strategy is needed that will allow the most frequently accessed operands to be kept in registers and to minimize register-memory operations．
Two basic approaches are possible，one based on software and the other on hardware．The software approach is to rely on the compiler to maximize register usage．The compiler will attempt to allocate registers to those variables that will be used the most in a given time period．This approach requires the use of sophisticated programanalysis algorithms．The hardware approach is simply to use more registers so that more variables can be held in registers for longer periods of time．
3．Characteristics of Reduced Instruction Set Architectures
Although a variety of different approaches to reduced instruction set architecture have been taken，certain characteristics are common to all of them．These characteristics are listed in Table 2．1 and described here．
The first characteristic listed in Table 2．1 is that there is one machine instruction per machine cycle．A machine cycle is defined to be the time it takes to fetch two operands from registers，perform an ALU operation，and store the result in a register．Thus，RISC machine instructions should be no more complicated than，and execute about as fast as，microinxtructions on CISC machines．[3] With simple，one –cycle instructions，there is little or no need for microcode；the machine instructions can be hardwired[4]．Such instructions should execute faster than comparable machine instructions on other machines，since it is not necessary to access a microprogram control store during instruction execution．
A second characteristic is that most operations should be register-to-register，with only simple LOAD and STORE operations accessing memory．This design feature simplifies the instruction set and therefore the control unit．For example，a RISC instruction set may include only one or two ADD instructions（e. g. ，integer add，add with carry）；the VAX has 25 different ADD instructions．Another benefit is that such an architecture encourages the optimization of register use，so that frequently accessed operands remain in high-speed storage．
Returning to Table 2-1，a third characteristic is the use of simple addressing modes．Almost all instructions use simple register addressing．Several additional modes，such as displacement and PC-relative，may be included．Other，more complex modes can be synthesized in software from the simple ones．Again，this design feature simplifies the instruction set and the control unit．
A final common characteristic is the use of simple instruction formats．Generally，only one or a few formats are used．Instruction length is fixed and aligned on word boundaries．Field locations，especially the opcode，are fixed．This design feature has a number of benefits.With fixed fields，opcode decoding and register operand accessing can occur simultaneously．Simplified formats simplify the control unit．Instruction fetching is optimized since word-length units are fetched．This also means that a single instruction does not cross page boundaries．
對(duì)高級(jí)語言程序執(zhí)行性能的研究已經(jīng)為設(shè)計(jì)新型處理器體系結(jié)構(gòu)－一精簡(jiǎn)指令系統(tǒng)計(jì)算機(jī)提供了指南。賦值語句占據(jù)的優(yōu)勢(shì)表明應(yīng)對(duì)單純的數(shù)據(jù)傳送進(jìn)行優(yōu)化。還有很多IF和LOOP指令存在，需要優(yōu)化基本的順序控制機(jī)構(gòu)，以使流水線作業(yè)高效率。操作數(shù)引用模式的研究表明，在多個(gè)寄存器中保存適當(dāng)數(shù)量的操作數(shù)，可以提高性能。
這些研究已經(jīng)形成了RISC機(jī)的一些關(guān)鍵特性：（1）有限的固定格式的指令集；（2）使用大量的寄存器或使用編譯器優(yōu)化寄存器應(yīng)用；（3）重點(diǎn)優(yōu)化指令流水線。
因?yàn)槊織l指令完成少數(shù)的且多為可預(yù)測(cè)的操作，RISC的簡(jiǎn)單指令系統(tǒng)適合高效流水線作業(yè)。RISC指令系統(tǒng)體系結(jié)構(gòu)也適合于延遲轉(zhuǎn)移技術(shù)，在這種技術(shù)中，隨同其他指令重新安排轉(zhuǎn)移指令以提高流水線效率。
雖然RISC系統(tǒng)已經(jīng)由不同的（企業(yè)）集團(tuán)以各種方式進(jìn)行了定義和設(shè)計(jì)，但大多數(shù)設(shè)計(jì)所提出的關(guān)鍵元素還是共同的。
l 用大量的通用寄存器（或使用編譯器技術(shù)）來優(yōu)化寄存器的使用；
l 有限的簡(jiǎn)單指令系統(tǒng)；
l 重點(diǎn)優(yōu)化指令流水線作業(yè)。
表2-1比較了幾種RISC和非RISC系統(tǒng)。
1．指令執(zhí)行特性
為了解RISC倡導(dǎo)者們的推理思路，首先觀察一下指令執(zhí)行的一些特性。所要關(guān)心的計(jì)算特性如下所述。
l 所完成的操作：這些操作決定了處理器要完成的功能和處理器與存儲(chǔ)器的交互
l 所用的操作數(shù)：操作數(shù)的類型和使用頻度決定了存儲(chǔ)操作數(shù)的存儲(chǔ)機(jī)制和訪問這些操作數(shù)的編址方式。
l 執(zhí)行順序：決定了控制和流水線的機(jī)制
2．大寄存器組的應(yīng)用
使用寄存器存儲(chǔ)的理由在于它是可用的最快的存儲(chǔ)器件，比主存儲(chǔ)器和高速緩存都快。寄存器組實(shí)際很小，通常與算術(shù)邏輯部件和控制器放在同一芯片上，而且使用比高速緩存和內(nèi)存儲(chǔ)器短很多的地址。因而需要一種允許最頻繁訪問的操作數(shù)保存在寄存器中并使寄存器-存儲(chǔ)器操作降至最少的策略。
有兩種可以采用的基本方法，一種基于軟件，一種基于硬件。軟件方法靠編譯程序最大限度使用寄存器，編譯程序力圖將給定時(shí)間周期內(nèi)最常用的那些變量分配到這些寄存器中。這一方法要求使用復(fù)雜的程序分析算法。硬件方法就是簡(jiǎn)單地使用更多的寄存器，使更多的變量保存在寄存器中供長(zhǎng)時(shí)間使用。
3．精簡(jiǎn)指令系統(tǒng)體系結(jié)構(gòu)的特性
盡管精簡(jiǎn)指令系統(tǒng)結(jié)構(gòu)的可用方法有多種，但對(duì)它們而言有一些特性是共同的。這些特性列在表2-1中，下面進(jìn)行解釋。
表2-1中列出的第一個(gè)特性是每個(gè)機(jī)器周期有一條機(jī)器指令。一個(gè)機(jī)器周期定義為，機(jī)器從寄存器組中取出兩個(gè)操作數(shù)，完成一種算術(shù)邏輯部件運(yùn)算并將結(jié)果存入一個(gè)寄存器中所用的時(shí)間。RISC機(jī)器指令應(yīng)該不比CISC機(jī)上的微指令復(fù)雜，并且執(zhí)行起來也很快。因?yàn)楹?jiǎn)單，單周期指令僅需少量或不需要微代碼；機(jī)器指令可以是硬連線的。這樣指令執(zhí)行起來比其他機(jī)器的類似機(jī)器指令要快，因?yàn)樵谥噶顖?zhí)行期間它不必訪問微程序控制存儲(chǔ)器。
第二個(gè)特性是，大多數(shù)操作應(yīng)該是寄存器對(duì)寄存器的，僅有簡(jiǎn)單的取（LOAD）和存（STORE）操作訪問存儲(chǔ)器。這種設(shè)計(jì)特點(diǎn)簡(jiǎn)化了指令系統(tǒng)，因而也簡(jiǎn)化了控制器。例如，一個(gè)RISC指令系統(tǒng)可以只包括一兩種加法（ADD）指令〔例如整數(shù)加，進(jìn)位加〕；VAX機(jī)則有25種不同的加法指令。另一好處是這種體系結(jié)構(gòu)促進(jìn)了對(duì)寄存器使用的優(yōu)化，使得頻繁訪問的操作數(shù)保存在高速存儲(chǔ)器中。
從表2-1還可看出第三個(gè)特性是采用簡(jiǎn)單的編址方式。幾乎所有指令都采用簡(jiǎn)單的寄存器編址。幾種附加的方式，如移位和與PC有關(guān)的方式可以包括進(jìn)去。另外，更為復(fù)雜的方式可以用簡(jiǎn)單的方式在軟件中合成。再次強(qiáng)調(diào)，這種設(shè)計(jì)特點(diǎn)簡(jiǎn)化了指令系統(tǒng)和控制器。
最后一個(gè)共同特性是采用簡(jiǎn)單的指令格式。一般來講，只使用了一種或少數(shù)幾種格式。指令長(zhǎng)度是固定的并按字的邊界調(diào)整。字段的位置，特別是操作碼的位置是固定的。這種設(shè)計(jì)有很多優(yōu)點(diǎn)，使用固定字段，操作碼譯碼和寄存器操作數(shù)訪問可同時(shí)進(jìn)行。簡(jiǎn)化的格式簡(jiǎn)化了控制器；因?yàn)槭前醋珠L(zhǎng)單位來讀取的，所以，取指令也得到優(yōu)化。這也表明一條指令不會(huì)跨頁。
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